Design, synthesis, and biological evaluation of indole-based 1,4-disubstituted piperazines as cytotoxic agents

Köksal, Meriç Akkoc | Yarım, Mine Yüksel | Durmaz, İrem | Çetin, Rengül Atalay

Article | 2012 | Turkish Journal of Chemistry36 ( 4 ) , pp.503 - 514

A series of 3-[(4-substitutedpiperazin-1-yl)methyl]-1H -indole derivatives were synthesized, and their structures were confirmed by spectral analysis. All the compounds were tested for their cytotoxic activity in vitro against 3 human tumor cell lines: human liver (HUH7), breast (MCF7), and colon (HCT116). Among the designed derivatives, most of the compounds showed significant cytotoxicity against liver and colon cancer cell lines with lower IC50 concentrations than the standard drug 5-fluorouracil. Compound 3s, with 3,4-dichlorophenyl substituent on the piperazine ring, was the most active in suppressing the growth of all screened . . . cancer cells Daha fazlası Daha az

Energy savings in simultaneous multi-threaded processors through dynamic resizing of datapath resources

Küçük, Gürhan | Mesta, Mine

Article | 2012 | Turkish Journal of Electrical Engineering and Computer Sciences20 ( 1 ) , pp.125 - 139

Nowadays, all the designers of systems from high-performance servers to battery-operated handheld devices aim for reliability, high-performance and longevity. Central within these aims the issue of processor power consumption is becoming increasingly important. In this study, we aim to adapt our already-provenmethod for single-threaded superscalar processors to simultaneous multi-threaded (SMT) processors for energy savings. The original method focused on resizing datapath resources according to the demands of running applications. To achieve this, the targeted resources are physically divided into multiple partitions, and turned on . . . and off according to the needs of the applications. Since, the energy consumption of the turned-off datapath resources is quite low, as a result, it becomes possible to have great amount of energy savings within a processor. However, special care must be taken when there are multiple threads racing against each other to gain access to shared datapath resources. As a result, our proposed microarchitectural technique achieves 0.5% Instructions Per Cycle (IPC) and 3.2% Total number of instructions Per Cycle (TPC) improvement, while it turns off 45% of the Reorder Buffer (ROB), 59% of the Load-Store Queue (LSQ), 43% of the Issue Queue (IQ), 30% of the integer Physical Register Files (PRF) and, finally, 48% of the floating PRF, on the average across all simulated benchmarks. According to our estimates, the total processor power is reduced by 12%, on the average Daha fazlası Daha az

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