Gören, S. | Gürsoy, C.C. | Yildiz, A.
Erratum | 2016 | Journal of Electronic Testing: Theory and Applications (JETTA)32 ( 1 ) , pp.105 - 106
[No abstract available]
Article | 2015 | Journal of Electronic Testing: Theory and Applications (JETTA)31 ( 05.06.2020 ) , pp.525 - 536
Today’s Integrated Circuit (IC) industry is suffering from piracy, overbuild ICs, and hardware Trojans. One way to protect ICs is logic locking. Logic locking is done by inserting extra logic to the original design’s netlist such that correct outputs are produced only when the correct key is applied. However, the determination of locations to insert logic is a computationally expensive process. In this paper, we propose a fault emulation technique to speed up the process of determination of fault locations. Our fault emulation technique enables dynamic multiple fault injection as well as real-time fault impact computation in a singl . . .e FPGA configuration. The effectiveness of the proposed emulation technique is evaluated with ISCAS’89 sequential benchmark circuits and results are presented. © 2015, Springer Science+Business Media New York