Detaylı Arama

Bulunan: 7 Adet 0.001 sn
- Eklemek veya çıkarmak istediğiniz kriterleriniz için 'Dahil' / 'Hariç' seçeneğini kullanabilirsiniz. Sorgu satırları birbirine 'VE' bağlacı ile bağlıdır.
- İptal tuşuna basarak normal aramaya dönebilirsiniz.
Bulunan: 7 Adet 0.001 sn
Koleksiyon [3]
Tam Metin [1]
Yazar [20]
Yayın Türü [1]
Konu Başlıkları [20]
Yayın Tarihi [6]
Dergi Adı [7]
Yayıncı [3]
Dil [2]
Yazar Departmanı [1]
A multi-channel real time implementation of Dual Tree Complex Wavelet Transform in field programmable gate arrays

Canbay, F. | Levent, V.E. | Serbes, G. | Ugurdag, H.F. | Goren, S. | Aydin, N.

Conference Object | 2016 | IFMBE Proceedings57 , pp.114 - 118

In medical applications, biomedical acquisition systems (BASs) are frequently used in order to diagnose and monitor critical conditions such as stroke, epilepsy, Alzheimer disease, arrhythmias and etc. Biomedical signals (BSs), which produce valuable information about the condition of various physiological subsystems in our body, can be obtained by using multi-channel BASs. Due to the time-varying behavior of physiological sub-systems, most of the BSs are expected to have non-stationary character. In order to derive desired clinical information from these non-stationary BSs, an appropriate analysis method which exhibits adjustable t . . .ime-frequency resolution is needed. The wavelet transform (WT), in which the time-frequency resolution can be adjusted according to the different parts of the signal, are widely used in the analysis of BSs. The discrete wavelet transform (DWT) is a fast and discretized implementation of classical WT and was employed as a feature extractor and de-noising operator for BSs in literature. However, due to the aliasing, lack of directionality and being shift-variance disadvantages, the DWT exhibits limited performance. A modified version of the DWT, which is named as Dual Tree Complex Wavelet Transform (DTCWT), is employed in the analysis of BSs and improved results are obtained. Therefore, in this study, considering the improvements in embedded system technology and the needs for wavelet based multi-channel real-time feature-extraction/de-noising operations in portable medical devices, the DTCWT is implemented as a multi-channel system-on-chip by using field programmable gate arrays. In proposed hardware architecture, for N input-channels, the DTCWT is implemented by using only one adder and one multiplier. The area efficiency and speed limits of proposed system are presented comparing with our previous approaches. © Springer International Publishing Switzerland 2016 Daha fazlası Daha az

Fast and Efficient Implementation of Lightweight Crypto Algorithm PRESENT on FPGA through Processor Instruction Set Extension

Varici, A. | Saglam, G. | Ipek, S. | Yildiz, A. | Goren, S. | Aysu, A. | Ugurdag, H.F.

Conference Object | 2019 | 2019 IEEE East-West Design and Test Symposium, EWDTS 2019 , pp.114 - 118

As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetric-key encryption algorithm for IoT devices. Compared to the Advanced Encryption Standard (AES), PRESENT uses a lower amount of resources while achieving the same level of security. In this paper, we implement PRESENT with different design methodologies including hand-coded RTL, Vivado HLS, PicoBlaze, VerySimpleCPU (VSCPU) based microcontrollers, and a customized VSCPU. The customized VSCPU design is based on optimizing the instruction set architecture for the algorithm specific . . .s of PRESENT. Our results show that the customized VSCPU design metholodogy can be more efficient than HLS and PicoBlaze while providing the flexibility compared to RTL designs. © 2019 IEEE Daha fazlası Daha az

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

Johnson, A.P. | Saha, S. | Chakraborty, R.S. | Mukhopadhyay, D. | Gören, S.

Conference Object | 2014 | Proceedings of the 9th Workshop on Embedded Systems Security, WESS 2014 , pp.114 - 118

1IEEE Council on Electronic Design Automation (CEDA);ACM Special Interest Group on Ada Programming Language (SIGAda);ACM Special Interest Group on Embedded Systems (SIGBED);ACM Special Interest Group on Microarchitectural Research and Processing (SIGMICRO);IEEE CAS;IEEE CS 9th Workshop on Embedded Systems Security, WESS 2014 -- 12 October 2014 through 17 October 2014 -- -- 108744

Software UART: A Use Case for VSCPU Worst-Case Execution Time Analyzer

Yildiz, A. | Iskender, D. | Ozlu, G. | Ugurdag, H.F. | Aktemur, B. | Goren, S.

Conference Object | 2019 | UBMK 2019 - Proceedings, 4th International Conference on Computer Science and Engineering , pp.504 - 509

This paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken by each function as output. A software UART system eliminates the need to employ a dedicated hardware for RS232 interface and makes directly use of the processor instead. For this purpose, we designed and implemented a memory-mapped system which has access to UART pins and is capable of setting and sampling these pins from software by a method of bit banging. We used the output of our WCET analyzer to approximate . . . the actual bit times for a specific UART baud rate. By successfully testing and verifying our software UART, we showed that our WCET analyzer could be used to estimate runtime of tasks in an application. Although development of the WCET analyzer is ongoing, the results are promising, © 2019 IEEE Daha fazlası Daha az

Fault emulation on heterogeneous architectures

Yildiz, A. | Gürsoy, C.C. | Gören, S.

Conference Object | 2017 | 2nd International Conference on Computer Science and Engineering, UBMK 2017 , pp.905 - 910

This paper presents implementation of fault emulation method which is very important in today's chip tests on a platform with heterogeneous architecture. Nowadays, the increase in the number of transistors in electronic circuits put fault emulation method forward which is faster than fault simulation in order to obtain a test set against possible defects on chips. In this method, a hardware model of the chip to be designed is implemented on Field Programmable Gate Arrays (FPGA) and it becomes possible to obtain a test set by applying different fault models. Heterogeneous architectures, on the other hand, provide energy savings and s . . .peed advantages over traditional architectural approaches as they involve different units in the execution of different workloads besides the central processing unit (CPU). Furthermore, multi-cycle tests are important because they can catch more errors with the same test vector than singlecycle tests. In this paper, as an application, it is explained the fault emulation of multi-cycle tests in a heterogeneous platform which employs FPGA and the results are shown. © 2017 IEEE Daha fazlası Daha az

Programmable hardware based short read aligner using Phred Quality scores

Gök, M.Y. | Sagiroglu, M.S. | Ünsalan, Cem | Gören, S.

Conference Object | 2013 | Proceedings - SocialCom/PASSAT/BigData/EconCom/BioMedCom 2013 , pp.864 - 867

Smith Waterman Algorithm is a widely used tool in bioinformatics. It aligns reads to a reference in whole genome sequencing. Mapping millions of sequences reads to a reference is a computationally expensive operation. Here, accuracy and performance are two important aspects of the process. Therefore, FPGA based solutions are widely used for this problem. In this study, we try to achieve a better mapping accuracy to achieve optimum alignment using Phred Quality scores of the bases of read sequences while keeping the performance high. We offer a new Smith Waterman processing unit and systolic array based on quality scores. © 2013 IEEE.

CPU Design Simplified

Yidiz, A. | Ugurdag, H.F. | Aktemur, B. | Iskender, D. | Goren, S.

Conference Object | 2018 | UBMK 2018 - 3rd International Conference on Computer Science and Engineering , pp.630 - 632

The first goal of this paper is to introduce a simple and customizable soft CPU named VerySimpleCPU (VSCPU), which could be easily implemented on FPGAs with a complete toolchain including instruction set simulator, assembler, and C compiler. The second goal is to offer to use this CPU as a teaching material within computer architecture/organization courses for students to understand the essentials and inner workings of a CPU better by designing a simple one. In addition to this, it is also aimed to teach writing code both in assembly level and C level for the CPU designed to understand what a compiler is and why it is needed. © 2018 IEEE.

6698 sayılı Kişisel Verilerin Korunması Kanunu kapsamında yükümlülüklerimiz ve çerez politikamız hakkında bilgi sahibi olmak için alttaki bağlantıyı kullanabilirsiniz.

Bu site altında yer alan tüm kaynaklar Creative Commons Alıntı-GayriTicari-Türetilemez 4.0 Uluslararası Lisansı ile lisanslanmıştır.