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Improving driver behavior using gamification

Helvaci, S. | Senova, A. | Kar, G. | Gören, S.

Conference Object | 2018 | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)10995 LNCS , pp.193 - 204

This work proposes a gamification approach to measure the driving behavior using the in-vehicle data and score drivers. Existing work largely focus on one functionality: either displaying vehicular info or scoring the driver. And some other work just provides navigation or Point of Interest (POI). In our work, we combine these features with minimal distraction for the driver. With this goal, we consider a system that interfaces to the vehicle bus and find the errors of the driver during the drive using multiple criteria. Furthermore, by providing achievements and leader boards, the driver is motivated to have a good score while driv . . .ing. To facilitate this analysis and to evaluate the system, we recorded two trips in real traffic. The results show that we achieve more than 95% accuracy between real-world scenario and the simulation. We also present POI feature that finds nearest preferred locations which are restaurants, hospitals, gas stations, pharmacies, car repair shops. © Springer International Publishing AG, part of Springer Nature 2018 Daha fazlası Daha az

An interdisciplinary approach in software engineering: Engineers meet designers [Yazılım Mühendisliğinde Disiplinler Arası Bir Yaklaşım: Mühendisler Tasarımcılar ile Buluşuyor]

Goularas, D. | Serif, T. | Gören, S.

Conference Object | 2018 | CEUR Workshop Proceedings2201 , pp.193 - 204

In this study, we examine the challenges that arise from an interdisciplinary collaboration in the field of Software Engineering through a common project between the undergraduate students of the Department of Computer Engineering and the Visual Communication and Design Department of Yeditepe University in Istanbul, Turkey. This collaboration between the two departments was carried out for two consecutive years. Each year a certain number of groups were formed including students from both departments. Every group had the objective to create a game as this type of application requires both design and computer programming skills. The . . .results reveal that this collaboration is beneficial for both students and instructors. From the students' point of view, the contact with people from different backgrounds prepares them for real-life situations. Additionally, this experience has also an education impact as it enables instructors to understand the difficulties students are facing, which as a result can be used as indicatory feedback to constantly improve the quality of the course Daha fazlası Daha az

VRLT: Cloud based highly scalable connected vehicle risk detection and life time estimation system

Bayraktar, S. | Gören, S.

Conference Object | 2018 | CEUR Workshop Proceedings2291 , pp.118 - 132

In this paper, we propose a cloud-based, scalable architecture for connected vehicle risk detection and life time estimation solution. Our conceptual solution collects real-time data from the vehicle itself by using mobile devices and from vehicle to vehicle (V2V) data generated by the cars in the traffic. OpenXC is the vehicle interface which enables a wide-range of real-time data collection from several points of the vehicle. With the help of a mobile device in the car V2V data can be obtained from the nearby vehicles such as approaching ambulance, motorcycle, sensor on the road etc. In the initial scope, we would to prevent accid . . .ents in the traffic. Accidents happen due to many situations in the traffic such as bad road conditions, broken vehicle parts, and poor driving habits. OpenXC and V2V data can be further merged, utilized in learning and prediction by using deep learning algorithms to detect early warnings to prevent accidents. By integrating further data systems such as weather conditions, vehicle service center logbooks and car manufacturers' repositories. Such additional data can be added to make stronger predictions for accidents and can further provide life time estimation of vehicle parts as a further benefit. © 2019 CEUR Workshop Proceedings.All Rights Reserved Daha fazlası Daha az

Development of a mobile news reader application compatible with in-vehicle infotainment

Kurt, B. | Gören, S.

Conference Object | 2018 | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)10995 LNCS , pp.18 - 29

People spend a lot of time behind the wheel every day. Reading newspapers while driving a car is almost impossible. In this work, a mobile news reader application is developed to deliver the latest news from various sources to the drivers. The major difference from other news reader applications is that it is developed in accordance with the Ford SYNC technology. The user will be able to view the latest news on the SYNC screen while driving and listening to the selected news. In addition, drivers can select the desired news source and the desired news with the voice commands. Therefore, our proposed news reader application is an ena . . .bler for the drivers to follow the news in a safe way without distraction while keeping their hands on the wheel and their eyes on the road. © Springer International Publishing AG, part of Springer Nature 2018 Daha fazlası Daha az

On optimization of multi-cycle tests for test quality and application time

Gursoy, C.C. | Yildiz, A. | Gören, S.

Conference Object | 2016 | Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016 , pp.18 - 29

Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing functional clock cycles of the test does not cause loss of detection of that fault. This paper presents a procedure that produces a multi-cycle test set by optimizing a single-cycle test set for fault coverage and test application t . . .ime while considering stuck-at, bridging and transition faults at the same time. © 2016 IEEE Daha fazlası Daha az

A Deep Learning Based Distributed Smart Surveillance Architecture using Edge and Cloud Computing

Kaşkavalci, H.C. | Gören, S.

Conference Object | 2019 | Proceedings - 2019 International Conference on Deep Learning and Machine Learning in Emerging Applications, Deep-ML 2019 , pp.1 - 6

Smart surveillance is getting increasingly popular as technologies become easier to use and cheaper. Traditional surveillance records video footage to a storage device continuously. However, this generates enormous amount of data and reduces the life of the hard drive. Newer devices with Internet connection save footage to the Cloud. This feature comes with bandwidth requirements and extra Cloud costs. In this paper, we propose a deep learning based, distributed, and scalable surveillance architecture using Edge and Cloud computing. Our design reduces both the bandwidth and as well as the Cloud costs significantly by processing foot . . .age prior sending to the Cloud. © 2019 IEEE Daha fazlası Daha az

Ultra-fast curve fitting for pulses on FPGA

Başaran, A. | Ugurdag, H.F. | Akdogan, T. | Güney, V.U. | Gören, S.

Conference Object | 2012 | 2012 20th Signal Processing and Communications Applications Conference, SIU 2012, Proceedings , pp.1 - 6

The hardware described in this work can process a pulse train out of a 1.5 GHz ADC and can summarize pulses with parameters such as amplitude, rise/fall times, and arrival time. It can handle back-to-back pulses with zero dead-time. The pulses can be as short as 9 samples. Such signals (and even many channels of it) can be found in high energy physics experiments, where particles are accelerated, collided, and detected. Similar physical setups are present in nuclear medical imaging, especially in positron emission tomography. We did the hardware implementation on FPGA. FPGAs offer tremendous parallelism and hence total compute power . . .. In this article, we present our top-level architecture, submodule details, design flow, and implementation details. Our FPGA design offers space, power, deployment time, and operational cost reduction in the respective applications. © 2012 IEEE Daha fazlası Daha az

Efficient Combinational Circuits for Division by Small Integer Constants

Ugurdag, H.F. | Bayram, A. | Levent, V.E. | Gören, S.

Conference Object | 2016 | Proceedings - Symposium on Computer Arithmetic2016-September , pp.1 - 7

Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of this problem, where the divisor is small and the circuit outputs a quotient and remainder. We propose a fast (low-latency) yet area-efficient combinational circuit topology, which we call Binary Tree based Constant Division (BTCD). BTCD uses a collection of small LUTs wired to each other to form a binary tree. The circuit also has bunch of adders, whose latencies are almost hidden as they operate in parallel with th . . .e binary tree. We wrote RTL code generators for BTCD and two previous works in the literature, then generated circuits for dividends of up to 128 bits and divisors of 3, 5, 11, and 23. We synthesized the generated RTL designs using a commercial ASIC synthesis tool. BTCD strikes a good balance between timing (latency) and area. It is up to 3.3 times better in Area-Timing Product (ATP) compared to the best alternative. ATP has a good correlation with energy consumption. © 2016 IEEE Daha fazlası Daha az

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

Johnson, A.P. | Saha, S. | Chakraborty, R.S. | Mukhopadhyay, D. | Gören, S.

Conference Object | 2014 | Proceedings of the 9th Workshop on Embedded Systems Security, WESS 2014 , pp.1 - 7

1IEEE Council on Electronic Design Automation (CEDA);ACM Special Interest Group on Ada Programming Language (SIGAda);ACM Special Interest Group on Embedded Systems (SIGBED);ACM Special Interest Group on Microarchitectural Research and Processing (SIGMICRO);IEEE CAS;IEEE CS 9th Workshop on Embedded Systems Security, WESS 2014 -- 12 October 2014 through 17 October 2014 -- -- 108744

Fault emulation on heterogeneous architectures

Yildiz, A. | Gürsoy, C.C. | Gören, S.

Conference Object | 2017 | 2nd International Conference on Computer Science and Engineering, UBMK 2017 , pp.905 - 910

This paper presents implementation of fault emulation method which is very important in today's chip tests on a platform with heterogeneous architecture. Nowadays, the increase in the number of transistors in electronic circuits put fault emulation method forward which is faster than fault simulation in order to obtain a test set against possible defects on chips. In this method, a hardware model of the chip to be designed is implemented on Field Programmable Gate Arrays (FPGA) and it becomes possible to obtain a test set by applying different fault models. Heterogeneous architectures, on the other hand, provide energy savings and s . . .peed advantages over traditional architectural approaches as they involve different units in the execution of different workloads besides the central processing unit (CPU). Furthermore, multi-cycle tests are important because they can catch more errors with the same test vector than singlecycle tests. In this paper, as an application, it is explained the fault emulation of multi-cycle tests in a heterogeneous platform which employs FPGA and the results are shown. © 2017 IEEE Daha fazlası Daha az

Reconfigurable hardware-based genome aligner using quality scores

Yagmur Gök, M. | Sagiroglu, M.Ş. | Ünsalan, Cem | Gören, S.

Conference Object | 2013 | 2013 21st Signal Processing and Communications Applications Conference, SIU 2013 , pp.905 - 910

Smith Waterman Algorithm is a widely used tool in bioinformatics to align reads from aligning to a reference in whole genome sequencing. Mapping millions of sequences read from sequencing is a computationally expensive operation. Accuracy and performance are two important aspects of this process. FPGA based solutions are widely studied. In this paper we tried to achieve a better mapping accuracy for optimum alignment using quality scores of the bases of read sequences while keeping the performance high. We are offering a new Smith Waterman processing unit and systolic array based on quality scores. © 2013 IEEE.

FPGA based particle identification in high energy physics experiments

Ugurdag, H.F. | Basaran, A. | Akdogan, T. | Guney, V.U. | Gören, S.

Conference Object | 2012 | Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors , pp.181 - 184

High energy physics experiments require on-the-fly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates to energy of the particle, while pulse occurrence times are needed for event reconstruction. Traditionally, these parameters have been extracted with the help of complete racks of dedicated electronics. Our FPGA design on a general-purpose DAQ card does real-time pulse detection and high-precision curve fitting. It greatly shrinks required equipment in terms of form factor, cost, power usage, and setup time. Unlike . . . traditional systems, we can handle bursts of back-to-back pulses, pulses as narrow as 6 ns and at rates over 1M pulses per second. We have a novel scalable architecture that combines pipelining and parallelism. Moreover, the parallel part of the architecture uses loop pipelining in each of its interleaved identical parallel processors (IIPPs). An IIPP is a specialized CPU, which executes nested loops, with number of iterations that varies from pulse to pulse. IIPPs are fed data from a FIFO by a priority encoder based dispatcher. Number of IIPPs can be calculated to meet any pulse rate and average pulse width. The architecture is flexible enough to work with a variety of curve fitting algorithms. © 2012 IEEE Daha fazlası Daha az

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